Patterning a device wafer is important in a variety of contexts, especially in the art of making semiconductor integrated circuit devices. As known in the art, the various features of a semiconductor integrated circuit device, such as the patterns of the interconnecting metallization lines and of the contact apertures in the insulating layers, must be patterned in accordance with the desired circuit configuration. For such patterning purposes, a tri-level resist system can be used, composed of a relatively thick bottom layer of suitable organic polymer material located upon the top surface of the device wafer to provide a smoothing of any irregularities of the wafer surface, a relatively thin intermediate layer of suitable inorganic material located upon the top surface of the bottom layer, and a top layer of suitable photosensitive resist (photoresist) material located upon the top surface of the intermediate layer. The intermediate layer acts as an etch stop to protect those portions of the bottom layer that are to remain in place for patterning the underlying wafer. For example, the bottom layer of the tri-level resist system is a spun-on organic photoresist layer, typically about 2.0 microns thick or less, of a material taken from a class of novalac-type photoresists such as those designated HPR-204 and HPR-206, manufactured by Phillip A. Hunt Chemical Corporation; the intermediate layer is silicon dioxide which has been plasma deposited to a thickness of about 0.12 micron; and the top layer is an azide-phenolic resin material, about 0.5 micron thick, such as AZ-2415 or MP-1400. A major advantage of this system stems from the fact that the top surface of the tri-level bottom layer is substantially planar even though the top surface of the semiconductor wafer is not, whereby the top surface of the top photoresist layer is likewise substantially planar as is desired for faithful optical imaging and hence for good control over the features in the ultimately patterned device (good linewidth control).
The tri-level resist system typically is used to pattern an underlying device wafer as follows. First, the top photoresist layer is patterned by (1) exposing it to an optical image pattern of light and dark areas, followed by (2) etching the top layer with a chemically selective etch that attacks and removes only the previously exposed light areas. Then, using the thus patterned top layer as a protective mask, the intermediate and bottom layers are patterned by an anisotropic reactive sputter etching step, whereby portions of the surface of the device wafer are exposed. By "anisotropic" it is meant that the patterning results in apertures being formed which have substantially vertical sidewalls in the intermediate and bottom layers. Using the remaining portion of the intermediate and bottom layers as a protective mask, the exposed portions of the surface of the device wafer are patterned as by another anisotropic reactive sputter etching step. Further illustrative details of tri-level resist systems can be found in U.S. Pat. No. 4,343,677 entitled "Method for Patterning Films Using Reactive Ion Etching Thereof," issued to E. Kinsbron et al on Aug. 10, 1982, and U.S. Pat. No. 4,244,799 entitled "Fabrication of Integrated Circuits Utilizing Thick High-Resolution Patterns," issued to D. B. Fraser et al on Jan. 13, 1981.
Prior to forming the intermediate layer upon the bottom layer, it is desirable to hard-bake the bottom layer to planarize (flow), harden and passivate it in order to prevent undesirable outgassing into the intermediate layer (forming pressure-induced cracks therein) and undesirable flow of the resist layer during deposition of the intermediate layer, as well as in order to render the bottom layer more opaque to the optical exposure wavelength, that is, the wavelength of the optical radiation used to form the image pattern in the top layer. Such exposure wavelength is ordinarily in the near ultraviolet region of the optical spectrum, typically in the approximate range of 300 to 400 nanometers; and it is desirable to suppress reflections of such radiation by the top surface of the wafer back into the top photoresist layer where such reflected radiation would otherwise produce undesirable standing waves which spoil the image. Thus, by making the bottom resist layer opaque to the exposure wavelength, the exposure radiation is absorbed therein, whereby production of the undesirable standing waves is prevented. On the other hand, it is also desired that the bottom resist layer be transparent to the wavelength of the optical alignment radiation, normally in the visible region of the spectrum and typically about 600 nanometers, which is subsequently used to align fiducial marks previously made on the top surface of the semiconductor device wafer (and hence also to align the top resist layer) at the proper position for subsequently focusing the optical image pattern in the top resist layer.
In prior art, the bottom resist layer has generally been hard-baked by a heat treatment in an oven chamber, maintained at temperatures of about 200 degrees C. for a time interval of about 2 hours. Such a time interval is unduly long, whereby the processing time is correspondingly undesirably prolonged, and moreover foreign particles in the chamber have an undesirably greater opportunity to contaminate the surface of the resist. Moreover, shortening the heat exposure time (to about 20 minutes) by maintaining the chamber at a higher temperature (about 240 degrees C.) tends to be impractical since it results in a subsequently deposited intermediate layer of silicon dioxide that suffers from an undesirable optical haze (not transparent) and an undesirably rough top surface (dimples and ridges).